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VHDL simulation of reset automatic block, 64 bit latch block, and test complete blocks for PD detection circuit system using FPGA

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dc.citedby0
dc.contributor.authorEmillianoen_US
dc.contributor.authorChakrabarty C.K.en_US
dc.contributor.authorGhani A.B.A.en_US
dc.contributor.authorRamasamy A.K.en_US
dc.contributor.authorid35974769600en_US
dc.contributor.authorid6701755282en_US
dc.contributor.authorid24469638000en_US
dc.contributor.authorid16023154400en_US
dc.date.accessioned2023-12-29T07:49:15Z
dc.date.available2023-12-29T07:49:15Z
dc.date.issued2010
dc.description.abstractThis paper is purely a model to determine the design circuit to implement Partial Discharge (PD) detection in FPGA technology. The research shall involve ISE Simulator version 10.1i (Xilinx) and ISE Xilinx Synthesized Technology (XST) using Very high integrated circuit Hardware Description Language (VHDL) programming to evaluate the use of Field Programming Gate Array (FPGA) for the detection and counting of partial discharge signals in high voltage underground cable. The impulse signals at the input data have very fast rise time in the range of 1 ns to 2 ns. The output signals of peak detector block, 64 bit BCD counter with reset block and reset automatic block is processed using reset automatic block and 64 bit latch block for keep output data in LCD to constant when the 64 bit BCD counter block is reset and return to zero again until update new data again. The combination of all blocks of PD detection circuit system is tested by using ISE simulator. In the next stage, this method will be implemented on a lab simulation scale for testing and validation. � 2010 IEEE.en_US
dc.description.natureFinalen_US
dc.identifier.ArtNo5562530
dc.identifier.doi10.1109/ICSGRC.2010.5562530
dc.identifier.epage19
dc.identifier.scopus2-s2.0-77957995643
dc.identifier.spage14
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-77957995643&doi=10.1109%2fICSGRC.2010.5562530&partnerID=40&md5=c6be657a6c4b937aae2e6ca46681aa43
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/30546
dc.pagecount5
dc.sourceScopus
dc.sourcetitleProceedings - ICSGRC 2010: 2010 IEEE Control and System Graduate Research Colloquium
dc.subjectADC with peak detector block
dc.subjectCounter with reset block
dc.subjectFPGA simulation
dc.subjectFPGA technology
dc.subjectPartial discharge detection
dc.subjectReal time processing
dc.subjectUnderground cable
dc.subjectVHDL programming
dc.subjectCables
dc.subjectComputer hardware description languages
dc.subjectField programmable gate arrays (FPGA)
dc.subjectPartial discharges
dc.subjectResearch
dc.subjectSignal detection
dc.subjectTechnology
dc.subjectUnderground cables
dc.subjectCounter with reset block
dc.subjectFPGA simulation
dc.subjectFPGA technology
dc.subjectPartial discharge detection
dc.subjectPeak detectors
dc.subjectRealtime processing
dc.subjectVHDL programming
dc.subjectDetectors
dc.titleVHDL simulation of reset automatic block, 64 bit latch block, and test complete blocks for PD detection circuit system using FPGAen_US
dc.typeConference paperen_US
dspace.entity.typePublication
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