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Implementation of PRINCE algorithm in FPGA

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dc.citedby15
dc.contributor.authorAbbas Y.A.en_US
dc.contributor.authorJidin R.en_US
dc.contributor.authorJamil N.en_US
dc.contributor.authorZ'aba M.R.en_US
dc.contributor.authorRusli M.E.en_US
dc.contributor.authorTariq B.en_US
dc.contributor.authorid56417806700en_US
dc.contributor.authorid6508169028en_US
dc.contributor.authorid36682671900en_US
dc.contributor.authorid24726154700en_US
dc.contributor.authorid16246214600en_US
dc.contributor.authorid57193327622en_US
dc.date.accessioned2023-05-29T06:00:44Z
dc.date.available2023-05-29T06:00:44Z
dc.date.issued2015
dc.descriptionAlgorithms; Application programs; Cryptography; Field programmable gate arrays (FPGA); Hardware; Hardware security; High speed cameras; Integrated circuit design; Logic Synthesis; Security of data; Throughput; Architectural modeling; Block ciphers; Cryptographic algorithms; Hardware implementations; PRINCE; Software implementation; Very high speed integrated circuits; VHDL; Computer hardware description languagesen_US
dc.description.abstractThis paper presents a hardware implementation of the PRINCE block cipher in Field Programmable Gate Array (FPGA). In many security applications, the software implementations of cryptographic algorithms are slow and inefficient. In order to solve the problems, a new FPGA architecture was proposed to speed up the performance and flexibility of PRINCE algorithm. The concurrent computing design allows an encryption block data of 64 bits within one clock cycle, reducing the hardware area and producing a high throughput and low latency. It also showed high speed processing and consumed low power. To do this, firstly, the encryption, decryption and key schedule are all implemented with small hardware resources, Next, an efficient hardware architectural model for PRINCE algorithms was developed using very high speed integrated circuit hardware description language (VHDL). Finally, the VHDL design for PRINCE algorithm was synthesized in FPGA boards. Two FPGA boards were used in this study, which are Virtex-4 and Virtex-6. The results show a throughput of 2.03 Gbps and efficiency of 2.126 Mbps/slice for Virtex-4, whereas a throughput of 4.18 Gbps and efficiency of 8.681 Mbps/slice for Virtex-6. � 2014 IEEE.en_US
dc.description.natureFinalen_US
dc.identifier.ArtNo7066593
dc.identifier.doi10.1109/ICIMU.2014.7066593
dc.identifier.epage4
dc.identifier.scopus2-s2.0-84937405931
dc.identifier.spage1
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-84937405931&doi=10.1109%2fICIMU.2014.7066593&partnerID=40&md5=91d5c300f5f56df56c00e9c09a3005e8
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/22398
dc.publisherInstitute of Electrical and Electronics Engineers Inc.en_US
dc.sourceScopus
dc.sourcetitleConference Proceedings - 6th International Conference on Information Technology and Multimedia at UNITEN: Cultivating Creativity and Enabling Technology Through the Internet of Things, ICIMU 2014
dc.titleImplementation of PRINCE algorithm in FPGAen_US
dc.typeConference Paperen_US
dspace.entity.typePublication
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