Publication:
Vth and ILEAK Optimization using taguchi method at 32nm bilayer graphene PMOS

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dc.citedby4
dc.contributor.authorNoor Faizah Z.A.en_US
dc.contributor.authorAhmad I.en_US
dc.contributor.authorKer P.J.en_US
dc.contributor.authorMenon P.S.en_US
dc.contributor.authorAfifah Maheran A.H.en_US
dc.contributor.authorid56395444600en_US
dc.contributor.authorid12792216600en_US
dc.contributor.authorid37461740800en_US
dc.contributor.authorid57201289731en_US
dc.contributor.authorid36570222300en_US
dc.date.accessioned2023-05-29T06:40:07Z
dc.date.available2023-05-29T06:40:07Z
dc.date.issued2017
dc.description.abstractA 32nm top-gated bilayer Graphene PMOS transistor was optimized and analyzed to find the optimum value of performance parameters besides investigating the process parameter that affects the performance of the bilayer Graphene transistor the most. Firstly, ATHENA and ATLAS modules which can be found in Silvaco TCADS Tools were employed to simulate the virtual device fabrication process and to confirm the electrical features of the device, respectively. L9 Taguchi robust analysis was then applied to enhance the device process parameters for the finest threshold voltage (VTH) and lowest leakage current (ILEAK) following the International Technology Roadmap for Semiconductor (ITRS) 2011 prediction. The parameters being optimized were the Halo implantation, Halo tilting angle, S/D implantation and compensation implantation which were varied at three levels and two levels of noise factor. The noise factors include sacrificial oxide layer temperature and BPSG temperature. The results of this work show that compensation implantation and Halo implantation are the most dominant factors in affecting the VTH and ILEAK respectively. Optimized results show an excellent device performance with VTH of -0.10299V which is 0.0097% closer to ITRS2011 target and ILEAK is 0.05545673nA/um which is far lower than the prediction.en_US
dc.description.natureFinalen_US
dc.identifier.epage109
dc.identifier.issue2-Jul
dc.identifier.scopus2-s2.0-85032973219
dc.identifier.spage105
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-85032973219&partnerID=40&md5=e53d52ecd21b5f940db0e7908457249c
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/23395
dc.identifier.volume9
dc.publisherUniversiti Teknikal Malaysia Melakaen_US
dc.sourceScopus
dc.sourcetitleJournal of Telecommunication, Electronic and Computer Engineering
dc.titleVth and ILEAK Optimization using taguchi method at 32nm bilayer graphene PMOSen_US
dc.typeArticleen_US
dspace.entity.typePublication
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