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Design of 0.13 micron MCML binary adders

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dc.contributor.authorChai Ming Kang
dc.date.accessioned2024-10-23T03:43:26Z
dc.date.available2024-10-23T03:43:26Z
dc.date.issued2014
dc.descriptionTK7868.D5 C42 2014
dc.description.abstractIn present days, most electronic devices are implemented static CMOS architecture due to its high speed operations, low static power dissipation, high noise margin and convenient availability in standard library cell. However, when running at high switching frequency, it dissipates large amount of dynamic power which drawback the performance of the electronic devices. Because power saving has become a major issue in electronic devices, recently a new logic style is evolved to cater the drawback of the static CMOS architecture, that is MOS Current Mode Logic (MCML) architecture. MCML is a new logic style that is seems to be promising in delivering high speed digital circuit applications such as smartphones and laptops, due to its constant power dissipation and high speed operations. This thesis reports the development of a MCML 4-bit binary adder at transistor and layout levels using Silterra's 0.13 micron CMOS process technology. A static CMOS 4-bit binary adder is also developed at transistor and layout levels to make comparisons between both architectures. The comparisons include pre-layout and post-layout simulations in terms of power, delay and area. Both adders are designed using Mentor Graphics' DA-IC at transistor level and IC Station at layout level, and simulated using ELDOSPICE.
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/34847
dc.language.isoen
dc.subjectDigital electronics
dc.titleDesign of 0.13 micron MCML binary adders
dc.typeResource Types::text::Final Year Project
dspace.entity.typePublication
oaire.citation.endPage77
oaire.citation.startPage1
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