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Design of MCML Multiplexer In 0.13 μm CMOS Technology

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dc.contributor.authorMohamad Izzat hanafie Bin Mohd Basiren_US
dc.date.accessioned2023-05-03T15:03:24Z
dc.date.available2023-05-03T15:03:24Z
dc.date.issued2019-10
dc.description.abstractThese few years, electronic devices play an important role in human life. They evolve from a big device to a portable device. The evolvement of this technologies were driven by the advancement of VLSI design, where the large circuit are now becoming smaller in size. Static CMOS design look very easy and simple to use, but it still not competent in term of speed and power. To solve the problem, MOS Current-Mode-Logic (MCML) architecture design is used. This architecture become popular because of its high performance in power and speed compared to CMOS. So, in this project, standard logic gate are being designed using MCML technology. The purpose of this project is to design 0.13μm Multiplexer using MCML technology and compare it with CMOS. The gates are designed using LtSpice software. Each gate will produce smaller dissipation power and propagation delay compared to CMOS.en_US
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/20510
dc.language.isoenen_US
dc.subjectMultiplexeren_US
dc.subjectMCMLen_US
dc.subjectElectronicen_US
dc.titleDesign of MCML Multiplexer In 0.13 μm CMOS Technologyen_US
dspace.entity.typePublication
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